FIELD OF THE INVENTION
The invention relates to a capacitor in a semiconductor configuration, in particular a DRAM configuration, having an electrode structure which contains a plurality of spaced-apart elements that are electrically connected to one another by a connecting structure, a capacitor dielectric, and a counterelectrode. The invention also relates to a process for producing a capacitor in a semiconductor configuration.
A multiplicity of integrated circuits require capacitors. Examples, besides the typical one of a dynamic memory cell, are analog/digital or digital/analog converters and filter circuits. Provisions are needed for reducing the intrinsically great amount of space that a capacitor requires, particularly with the miniaturization of structures involved in the increased scale of integration or since chip area has to be economized upon. A typical example may be considered to be the dynamic semiconductor memory, in which the required area of the usually used single-transistor memory cell is reduced from one memory generation to another with increasing memory density. At the same time, the minimum capacitance of the memory capacitor must be preserved.
In dynamic semiconductor configurations, a single-transistor memory cell includes a readout transistor and a capacitor. By triggering the readout transistor through a word line, the information, that is the electric charge, stored in the capacitor can be read out through a bit line. The memory capacitor must have a minimum capacitance in order to provide reliable storage of the charge and simultaneous capability of distinguishing the read-out information. The lower limit for the capacitance of the memory capacitor is currently considered to be 20 fF. In order to attain that capacitor capacitance, the thickness of the dielectric must be as small as possible and the area of the capacitor as large as possible.
While up to the 1 Mbit memory generation, it has been possible to realize both the readout transistor and the capacitor in the form of planar components, from the 4 Mbit memory generation on configurations are known in which the capacitor is disposed in a trench (trench capacitor). The electrodes of the capacitor are disposed along the surface of the trench. Overall, that yields an effective surface area of the capacitor which is increased as compared with a planar configuration on the surface of the substrate.
A further option for increasing the capacitance with an unchanged changed or reduced space requirement for the capacitor is to construct the capacitor as a stacked capacitor. Through the word lines, a polysilicon structure, for instance a crown structure or a cylinder, is formed that is contacted with the substrate. The polysilicon structure forms a memory node that is provided with the capacitor dielectric and the capacitor plate or so-called cell plate. That concept has the advantage of being compatible with a logic process.
The free space above the substrate surface is used for the capacitor. The entire cell surface can be covered with the polysilicon structure, as long as the structures of adjacent memory cells are isolated from one another. Known configurations along those lines are the fin stacked capacitor and the crown stacked capacitor.
A semiconductor memory configuration with a stacked capacitor as the memory capacitor is known from Published European Patent Application 0 415 530 A1. The stacked capacitor includes a polysilicon structure with a plurality of polysilicon layers, stacked substantially parallel to each other and joined together through at least one lateral support. The lateral support is produced with the aid of a polysilicon layer that is subsequently etched back, so that a substantially upright land remains that joins the polysilicon layers which are stacked one above the other. The structure is formed by alternatingly depositing polysilicon layers and silicon oxide layers, which are etchable selectively to them, on the surface of the substrate, by structuring those layers, by producing the lateral supports on at least one side of the structure, and by selective etching out of the silicon oxide layers. The polysilicon structures are arsenic-doped. Next, silicon oxide is formed by thermal oxidation as the capacitor dielectric, over which the cell plate of doped polysilicon is deposited. In a capacitor with stacked electrode layers which is known from U.S. Pat. No. 5,240,871, variously rapidly etching isolation layers are applied over a polysilicon layer. The isolation layers are then structured and etched, producing a support framework. Subsequently, doped polysilicon is deposited and then a silicon nitride layer, followed by the formation of the cell plate.